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As printed circuit board (PCB) track geometries shrink, sometimes it becomes necessary to look deeper than the material data sheet when modelling electrical properties of transmission lines; this study looks at how variation in dielectric constant should be handled in multiple and single dielectric PCB builds. This paper describes how even FR4 builds should in some cases be treated as multiple dielectric builds. Approaches for understanding the root cause of effective dielectric constant variation with structure, coupling and scale are considered. An outline of the implementation of the boundary element method is provided for those wishing to look a little deeper into the modelling process. Finally, a brief investigation covers the sources of measurement errors aimed at helping to put the best data back into the modelling process.

The purpose of this paper is to discuss nickel gold plating of PCB traces and its adverse effects on signal integrity, and to explore the other key drivers in optimising yields and controlling PCB processes that impinge on signal integrity.

The paper is a response to requests from PCB fabricators to explain why the losses on impedance controlled traces on PCBs were sometimes higher than expected.

While nickel is acceptable on short lengths of pad to accommodate gold plating, plating the whole trace length is generally not good practice from a digital signal integrity perspective. In addition, with the fastest serial transmission rates in the 10 to 20 GHz region and long serial words in some situations designers may need to consider both the associated high and low frequency performance.

With the development of ultra high speed digital bus architectures, PCB fabricators will appreciate the need to add an understanding of the drivers of insertion loss (base material loss tangent data, foil roughness and copper cross sectional areas) to their existing experience of architectures with minimal losses.

The aim of this paper is to demonstrate that root impulse energy (RIE) testing is a practical and robust “go/no go” test technique for PCB material losses that can be deployed on the PCB production floor.

The study used the RIE method, employing time domain reflectometry techniques on industry standard impedance test coupons modified to include short reference lines and longer test lines. Practical considerations for the use of the methodology on the production floor, such as coupon design, probe layout and environmental conditions were investigated.

RIE with a 250 ps reflected risetime appears suitable for discerning significant differences in material loss properties provided proper coupon design is incorporated into the panel design and frequencies of interest are limited to a limit commensurate with high reliability and repeatability.

The RIE test proposed does not replace conventional impedance control techniques that are currently in use. However, a suitable standard for loss and cross test equipment calibration is key and will need to be established before this new measurement technique can gain widespread trust throughout the industry.

The paper shows RIE testing is a practical and achievable test method; it is easily deployed and offers repeatable, reliable discrimination between PCBs fabricated with a range of varying base material loss characteristics.